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Clients in the News
Optimal in Advanced Packaging, Industry Voices (4/06)
Design for Yield — A Hot Term for an Old Concept
by Len Perham
"Achieving design for yield (DFY) has more to do with effectively managing the IC design process than it does
with introducing a new generation of software tools."
http://ap.pennnet.com/Articles/Article_Display.cfm?Section=ARTCL&ARTICLE_ID=252776&VERSION_NUM=2&p=36
Sagantec in Semiconductor International (2/1/06)
We Know We Need DFM; How Do We Get There?
by Coby Zelnik, Executive Vice President, Sagantec
"Design for manufacturing (DFM) is the hot buzzword in chip design circles. Triggered by the commercial deployment of new
semiconductor process technologies at 90 nm and below, chip designers and their managers finally have to concede that they now have to design their chips with
manufacturability at the top of their minds."
http://www.reed-electronics.com/semiconductor/article/CA6302629?text=zelnik
Optimal in EDACafe (EDAWeekly Review) (11/21-25/05)
The Optimal Solution
by Jack Horgan
"The weekly editorials have covered several vendors in the power integrity field. Some have attacked the issue through power management
and some though power grid design. Optimal offers products with complete signal integrity and power integrity design flow from IC to
Package to PCB."
http://www10.edacafe.com/nbc/articles/view_weekly.php?articleid=224585
Sagantec in Electronic Design (11/7/05)
Process Migration for IP and ASICS
by Coby Zelnik
"Upon completion of an ASIC design, unexpected results often appear because
they weren't predicted accurately by the design tools. For instance, the chip
size may be too large, the circuit may not clock fast enough, or it may consume
too much power. Rather than redesign the chip, another option might be to use
automatic process migration. This design-automation methodology takes a finished
physical layout and automatically converts it to another set of process design
rules, enabling it to be fabricated in a new target process technology."
http://www.elecdesign.com/Articles/Print.cfm?ArticleID=11343
Optimal in Electronic Design(10/13/05)
Packaging Rides the Z Axis into the Third Dimension
by Roger Allan
"Demands for lower-cost, higher-density, and smaller-footprint ICs aimed at portable electronics make 3D-packaging
designers sweat."
http://www.elecdesign.com/Articles/Print.cfm?ArticleID=11179
San Jose State University, College of Engineering and eSilicon in Electronic News(4/8/05)
Breakfast in the Valley: Engineering Education on the Rocks
by Ed Sperling
"Electronic News sat down to discuss the future of engineering education in the United States with
Jack Harding, chairman and CEO of eSilicon; Jim Hogan, general partner at Telos Venture Partners, and Belle Wei,
dean of the College of Engineering at San Jose State University."
http://email.electronicnews.com/cgi-bin2/DM/y/elfm0KDLln0DbD0CSoD0EU
Optimal in Electronic Design (2/3/05)
Power Integrity Comes Home To Roost At 90 nm
by David Maliniak
"IC designers moving to 90-nm processes can place power integrity atop their list of most worrisome design issues."
http://www.electronicdesign.com/Articles/ArticleID/9548/9548.html
Optimal, eSilicon, and SI2 in Electronic News (1/27/05)
Special Market Focus: Collaborative Design
by Ann Steffora Mutschler
"More than anything else, complexity and outsourcing are the power behind the rising wave of collaborative design."
http://www.reed-electronics.com/electronicnews/article/CA499446.html
Nassda in EE Times (1/24/05) "Crosstalk"
Better suggestions for growing the EDA pie
by Graham Bell, Senior Director of Marketing, Nassda Corp.
http://eetimes.com/news/latest/showArticle.jhtml?articleID=57702499
Optimal in EE Times (1/17/05)
Power tool unites package, pcb
by Richard Goering
"Printed-circuit-board designers are having severe problems with IC packages that don't work once they're placed on a board.
Optimal Corp. this week will offer a solution with PowerGrid, a power integrity analysis tool aimed at designers of both IC packages and
pc boards."
http://www.eetimes.com/article/showArticle.jhtml?articleId=57701383
Optimal and Nassda in Electronic News (10/8/04)
If They Come, Can You Build It?
by Ed Sperling
"Electronic News sat down to discuss design for manufacturability and whether the concept works with Len Perham,
CEO of Optimal; Vincent Tong, VP of product technology for Xilinx's advanced products group; Walter Ng, senior director
of design solutions at Chartered Semiconductor; and Graham Bell, senior director of marketing at Nassda."
http://www.reed-electronics.com/electronicnews/article/CA470198
Optimal in EEDesign (8/20/04)
Riding the 'wave' of 90nm signal integrity
by Ching-Chao Huang, Senior Vice President, Optimal Corp.
http://www.eetimes.com/news/design/showArticle.jhtml?articleID=26807284
Optimal in EDN (8/19/04)
Signal integrity needs to be unified across the board at 90nm
by Len Perham, Chairman and CEO of Optimal Corp.
http://www.reed-electronics.com/ednmag/article/CA446158?industryid=2813&nid=2017&rid=1921749787
Optimal in EETimes (4/26/04)
Full-wave analysis tools target 2 GHz+
by Mike Santarini
http://www.eetimes.com/showArticle.jhtml?articleID=18902623
Optimal in EEDesign (2/23/04)
Using S parameters for signal integrity analysis
by Ching-Chao Huang, Senior Vice President, Optimal Corp.
http://www.eedesign.com/news/showArticle.jhtml?articleID=18100057
Optimal in EETimes (12/8/03)
Speedy FPGAs need IC/package co-design
by Paul Y.F. Wu, packaging design manager, and Soon Chee, advanced-package development manager, at
Xilinx; Ching-Chao Huang, Senior VP at Optimal
http://www.eetimes.com/in_focus/mixed_signals/OEG20031208S0079
Runtime in Chip Design Magazine article (10/03)
Flow Management Tool Tracks Files
by Elliot Koch and Michael Grossman of Virtual Silicon
"In contrast, advanced flow-management tools like those from Runtime Design Automation automatically
identify dependencies....This capability means that an engineer can add a new tool to a flow simply
by running the tool and allowing the flow-management software to capture its dependencies."
http://www.chipdesignmag.com/display.php?articleId=45&issueId=1
Sagantec in EDA Weekly column (5/26/03)
by Peggy Aycinena
"Coby Zelnik, Senior Vice President of Business Development at Sagantec
North America, Inc....said, 'At Sagantec, we believe that current
analog design techniques and the people behind them are indispensible.
EDA needs to accelerate their tasks and help them be more productive,
but at the same time, preserve their skills and creativity.'"
http://www.edacafe.com/
magazine/index.php?
run_date=26-May-2003&
newsletter=1
Nassda in EE Times article (5/5/03)
Timing tool is both static and dynamic
by Richard Goering
"Claiming the first hybrid approach to transistor-level timing and
crosstalk analysis, Nassda Corp. this week will introduce Hanex, a
product that combines static and dynamic analysis techniques. Aimed
at full-custom design, Hanex finds critical paths..."
http://www.eetimes.com/news/design/showArticle.jhtml?articleID=17408383
Nassda in Deepchip (9/10/02)
by John Cooley
"This year's golden boy in the Near SPICE niche has been Nassda. Not only does their HSIM do well..."
http://www.deepchip.com/items/dac02-20.html
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