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Technology Leadership
Atrenta in EDN, (8/15/2010)
The time is now for 3-D stacked die
by Rick Nelson, Chief Editor
"As the semiconductor industry moves from 'more Moore' to 'more than Moore,' 3-D-stacked-die implementations will become critical for implementing
ever-denser chip packages."
http://www.edn.com/article/509643-The_time_is_now_for_3_D_stacked_die.php
Atrenta in System-Level Design, (7/22/2010)
'Good' Vs. 'Good Enough'
by Ed Sperling
"The decision for when a chip is ready for tapeout is changing—both in time and sometimes in terms of who's actually making that decision—as the amount of software being developed by hardware companies continues to grow."
http://chipdesignmag.com/sld/blog/2010/07/22/good%e2%80%99-vs-%e2%80%98good-enough%e2%80%99/
Atrenta in Test & Measurement World, (6/15/2010)
Atrenta hosts 3-D SoC design flow demo
by Rick Nelson
"Atrenta, AutoESL, Qualcomm, and IMEC have been collaborating on 3-D chip design, and they demonstrated what might be called a working prototype front-end 3-D
chip design system June 14 at the Design Automation Conference at Atrenta's booth."
http://www.tmworld.com/blog/Taking_the_Measure/39312-Atrenta_hosts_3_D_SoC_design_flow_demo.php
Atrenta in EDACafe, (10/29/2009)
Technical Paper: Verification of Multi-Clock Designs
"This white paper outlines a holistic approach to resolving issues associated with ever increasing numbers of clock interfaces, where data is
transferred between clocks of different frequencies and often between asynchronous domains."
http://www10.edacafe.com/link/display_detail.php?link_id=29617
Atrenta in Low-Power Engineering, (6/10/2010)
Experts at the Table: Nice to Have Vs. Need to Have
"Complexity is driving need to have for better up-front planning, better IP re-use, more things like verification IP and standards interfaces."
http://chipdesignmag.com/lpd/blog/2010/06/10/experts-at-the-table-nice-to-have-vs-need-to-have/
Atrenta in System-Level Design, (6/2/2010)
Experts at the Table: Problems to Solve in 3D Stacking
by Ed Sperling
"The mainstream world is not starting to think about 3D yet, but the large companies have either done it or are actively thinking about it."
http://chipdesignmag.com/sld/blog/2010/06/04/experts-at-the-table-problems-to-solve-in-3d-stacking-3/
Atrenta in IC Design and Verification Journal, (6/1/2010)
Escaping from the Silo: Fixing the 'Anti-Social' World of EDA Tools
by Ron Craig, Senior Marketing Manager Atrenta
"As a chip designer and EDA tool user, it's imperative to see the broader picture when using any tool which modifies your design in any way.
If the tools you are using aren't playing ball, maybe it's time to ask for better tools."
http://icjournal.com/icjournal/articles/20100601-atrenta/
Atrenta in EDA DesignLine, (5/26/2010)
Atrenta, AutoESL claim working 3D design flow
by Anne-Francoise Pele
"…the design flow is presented as the early version of a working system that addresses 3D-aware high-level synthesis, early partitioning, floorplanning
and multi-domain analysis."
http://www.edadesignline.com/showArticle.jhtml?articleID=225200219
Atrenta in System-Level Design, (5/21/2010)
Experts At The Table: Problems To Solve In 3D Stacking
by Ed Sperling
"The business need and the technical need for 3D is real.…When you look at the complexity on one side and the parasitics on the other, both of those
say you need to have some sort of 3D technology moving forward. The process enhancement has been happening and 3D technology is coming to the point where
it can become mainstream."
http://chipdesignmag.com/sld/blog/2010/05/21/experts-at-the-table-problems-to-solve-in-3d-stacking/
Atrenta in System-Level Design, (4/22/2010)
Timing Bomb
by Ed Sperling
"Timing closure, a basic operation in chip design and development, is becoming anything but basic at advanced process nodes."
http://chipdesignmag.com/sld/blog/2010/04/22/timing-bomb/
Atrenta in Chip Design, (3/2010)
SoC Designers Must Have Tangible Quality Metrics for Semiconductor Intellectual Property
by Piyush Sancheti, Senior Director of Business Development
"Simply stated, there are two major classes of design quality. A design or IP must meet its functional requirements and adhere to the protocol or
spec which it was intended for. But also, the IP must successfully integrate with the chip or sub-system it is was designed for."
http://chipdesignmag.com/display.php?articleId=4028
Atrenta in Chip Design, (2-3/2010)
Power-Optimization Solution Serves Ubiquitous RTL Designer
by Kiran Vittal, Product Marketing Director Atrenta
"Today's power-smart RTL designers use an “explicit enable
signal" coding style in their VHDL or Verilog designs.
This approach allows power-synthesis tools to insert clockgating
logic on these explicit enables. However, such tools
do not do the computation of the differential power savings
for each enable."
Excerpt from Chip Design Magazine Feb-Mar 2010
Altos Design Automation in Chip Design, (2/16/2010)
Thanks for The Memories But…
by Jim McCanny, CEO Alto Design Automation
"For challenging low-power and/or high performance designs, instance based characterization is a requirement to get the most out of the under-lying
silicon process and to truly manage timing and power. In short, tell you’re your IP supplier thanks for the memories, no thanks for the models and
take charge of creating the memory models you need yourself."
http://chipdesignmag.com/display.php?articleId=3947
Atrenta in EDA DesignLine, (2/10/2010)
EDA: Aging or dying?
by Mike Gianfagna, VP Marketing Atrenta
"It is unreasonable to believe that the current technology revolution in the consumer market will continue while EDA dies. Let's agree to stop
predicting the death of this important business and rather debate how it will mature (and grow)."
http://www.edadesignline.com/showArticle.jhtml?articleID=222700693
Atrenta in EDA DesignLine, (2/10/2010)
EDA DesignLine Engineering Guest Blog
by Mike Gianfagna, VP Marketing Atrenta
"EDA: Aging or dying?...It is unreasonable to believe that the current technology revolution in the consumer market will continue while EDA dies.
Let's agree to stop predicting the death of this important business and rather debate how it will mature (and grow)."
http://www.edadesignline.com/guest_
blogs/;jsessionid=5C5AQ4KCXS1B
1QE1GHRSKHWATMY32JVN
Altos Design Automation in Chip Design, (1/2010)
Designers—Start Your Characterization Engines
by Jim McCanny, CEO Altos Design Automation
"To get the most out of process technologies coming on line right now, designers need to radically re-think their strategies for timing closure.
The additional burdens of accounting for process variability, managing leakage and hitting a low power budget make obtaining market leading performance extremely difficult."
http://chipdesignmag.com/display.php?articleId=3893
Paul McLellan in Electronic Design (1/7/10)
To Shake Its Malaise, EDA Must Look To Where Design Is Really Happening
by Paul McLellan
"EDA is in trouble. It has become a fat change-averse business in a fast-changing environment. Even as the electronic system market is growing strongly, it is fragmenting."
http://electronicdesign.com/content.
aspx?topic=to_shake_its_malaise_
eda_must_look_to_where_design_
is_really_happening&catpath=eda
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