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Technology Leadership
Atrenta in System-Level Design, (3/31 and 4/15/2011)
Experts At The Table: EDA's Next Challenges
by Ed Sperling
"System-Level Design sat down to discuss the future of EDA with Neil Hand, group director for product marketing in Cadence's new business group;
Mike Gianfagna, vice president of marketing at Atrenta; and Johnson Teng, COO at Springsoft. "
Part 1: http://chipdesignmag.com/sld/blog/2011/03/31/experts-at-the-table-edas-next-challenges/
Part 2: http://chipdesignmag.com/sld/blog/2011/04/15/experts-at-the-table-eda%E2%80%99s-next-challenges/
Video: http://www.youtube.com/watch?v=IYA2o0tzOZs&feature=youtu.be
Atrenta in Semiconductor Manufacturing & Design, (2/14, 25 and 3/14/2011)
Experts At The Table: 3D Stacking
"Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at
Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon
Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice president of marketing at Atrenta."
Part 1: http://semimd.com/blog/2011/02/14/experts-at-the-table-3d-stacking/
Part 2: http://semimd.com/blog/2011/02/25/experts-at-the-table-3d-stacking-2/
Part 3: http://semimd.com/blog/2011/03/14/experts-at-the-table-3d-stacking-3/
Atrenta in Low-Power Engineering, (2/10, 18, 25/2011)
Experts At The Table: Concurrent Design
"Low-Power Engineering sat down with Marco Brambilla, ASIC design manager at STMicroelectronics; Charlie Janac, president and CEO of Arteris; Mike Gianfagna,
vice president of marketing at Atrenta, and Javier DeLaCruz, director of semiconductor packaging at eSilicon."
Part 1: http://chipdesignmag.com/lpd/blog/2011/02/10/experts-at-the-table-concurrent-design/
Part 2: http://chipdesignmag.com/lpd/blog/2011/02/18/experts-at-the-table-concurrent-design-2/
Part 3: http://chipdesignmag.com/lpd/blog/2011/02/25/experts-at-the-table-concurrent-design-3/
Atrenta in EE Times, (2/1/2011)
DesignCon panel mulls over delayed design skeds
by Nicolas Mokhoff
"At DesignCon here a panel of four designers from Broadcom, Nvidia, Netlogic, and Juniper Networks, agreed that designs need to meet different
'good enough' specs for different markets. The panelists gathered to discuss what methodologies could speed up design schedules. They agreed that design
cycles vary across design teams and the design windows for one type of design are markedly different from that of another."
http://www.eetimes.com/electronics-news/4212738/DesignCon-panel-mulls-over-delayed-design-skeds?cid=NL_EETimesDaily
Atrenta in Chip Design, (1/27/2011)
Soft IP quality - who owns it? Chip Design HOME PAGE
by Piyush Sancheti, Atrenta Inc.
"Depending on how you look at it, the good or bad news is that IP quality is really owned by all major constituencies in the semiconductor supply
chain, including IP vendors, chip and system companies, foundries and EDA vendors."
http://chipdesignmag.com/display.php?articleId=4666
Atrenta in IC Journal, (1/4/2011)
Timing Closure in 2011: What Is the Key?
by Ron Craig, Atrenta Inc. and Bob Smith, Magma Design Automation
"…timing closure in the backend is no longer working – that this “tortoise” will indeed eventually get there, but at what cost? Is there a way to add certainty to the process?"
http://www.techfocusmedia.net/icjournal/articles/20110104-timing/
Jim Hogan and Paul McLellan in EDA360 Insider, (1/3/2011)
Deconstructing EDA360: Paul McLellan writes about the evolution of SoC design methodology in the era of re-aggregation
by Steve Leibson, EDA360 Evangelist and Marketing Director at Cadence Design Systems
"…SoCs have become, first and foremost, software-execution machines. They are processor heavy and the bulk of the effort in developing systems based on such SoCs is in the
software development…. Therefore, any SoC design methodology must include a way to model an SoC in sufficient detail for meaningful hardware development on a virtual platform
while allowing deep dives into lower modeling abstraction levels when more simulation detail is needed."
http://eda360insider.wordpress.com/2011/01/03/deconstructing-eda360-paul-mclellan-writes-about-the-evolution-of-soc-design-methodology-in-the-era-of-re-aggregation/
Altos Design Automation in Low-Power Engineering, (12/2-17/2010)
Experts At The Table: IP Integration Hurdles (3 parts)
by Ed Sperling
"Low-Power Engineering sat down to discuss IP integration issues with Ken Brock, senior staff product marketing manager for logic libraries in Synopsys'
Solutions Group; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Jim McCanny, CEO of Altos Design Automation."
Part 1: http://chipdesignmag.com/lpd/blog/2010/12/02/experts-at-the-table-ip-integration-hurdles/
Part 2: http://chipdesignmag.com/lpd/blog/2010/12/10/experts-at-the-table-ip-integration-hurdles-2/
Part 3: http://chipdesignmag.com/lpd/blog/2010/12/17/experts-at-the-table-ip-integration-hurdles-3/
Altos Design Automation in Low-Power Engineering, (12/1/2010)
The Trouble With Semiconductor IP (Video)
"Low-Power Engineering takes a poll of the big problem with IP and how to solve it from Ken Brock, senior staff product marketing manager at Synopsys; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna,
vice president of marketing at Atrenta, and Jim McCanny, CEO of Altos Design."
http://chipdesignmag.com/lpd/blog/2010/12/01/the-trouble-with-semiconductor-ip/
Atrenta in Test & Measurement World, (11/17/2010)
SOC DFT verification with static analysis and formal methods
"You can meet the challenges of verifying the connectivity of system-on-chip designs at the RTL and netlist level for both functional and test modes."
by Marco Brambilla and Jean PhillippeLoison, STMicroelectronics; Kiran Vittal, Atrenta
http://www.tmworld.com/article/511569-SOC_DFT_verification_with_static_analysis_and_formal_methods.php
Atrenta in EETimes, (11/4/2010)
Will IP use increase in forthcoming SoC design?
by Piyush Sancheti, senior director of business development
"Whether developed internally by a central group or acquired from a commercial vendor, the use of IP allows you to focus on things you differentiate on and to farm
out all other general purpose blocks. Studies have shown that an effective IP strategy can cut down the overall SoC design effort by as much as 50-60 percent."
http://www.eetimes.com/discussion/other/4210404/Will-IP-use-increase-in-forthcoming-SoC-design-
Altos Design Automation in Chip Design, (11/1/2010)
IP Characterization Moves from The Backroom
by John Blyler, Editorial Director
"The increased quantity and complexity of IP needed for today's SoCs mean that IP integrators must verify and understand the affects of modifying vendor IP.
Chip Design magazine sat down to discuss the expanding role of IP characterization in SoC design with Jim McCanny, CEO of Altos Design Automation. "
http://chipdesignmag.com/display.php?articleId=4504
Atrenta in Low-Power Engineering, (10/7–22/2010)
Experts At The Table: Timing Constraints
by Ed Sperling
"Low-Power Engineering sat down to discuss timing constraints with ARM Fellow David Flynn; Robert Hoogenstryd, director of marketing for design analysis and signoff
at Synopsys; Michael Carrell, product marketing for front end design at Cadence; Ron Craig, senior marketing manager at Atrenta; and Himanshu Bhatnagar,
executive director of VLSI design at Mindspeed Technologies."
Part 1: http://chipdesignmag.com/lpd/blog/2010/10/07/experts-at-the-table-timing-constraints/
Part 2: http://chipdesignmag.com/lpd/blog/2010/10/15/experts-at-the-table-timing-constraints-2/
Part 3: http://chipdesignmag.com/lpd/blog/2010/10/22/experts-at-the-table-timing-constraints-3/
Atrenta in EDN, (8/15/2010)
The time is now for 3-D stacked die
by Rick Nelson, Chief Editor
"As the semiconductor industry moves from 'more Moore' to 'more than Moore,' 3-D-stacked-die implementations will become critical for implementing
ever-denser chip packages."
http://www.edn.com/article/509643-The_time_is_now_for_3_D_stacked_die.php
Atrenta in System-Level Design, (7/22/2010)
Why Open Source Matters
by Ann Steffora Mutschler
"In the end, for software virtual prototypes to proliferate, there must be a rich library of IP models to drive the whole process.
'Some will come from the larger IP suppliers, but many will be missing,' Gianfagna said. 'An open source development environment
holds the promise to plug this hole. There are plenty of examples of rich capability that has resulted from open source
collaboration, why not semiconductor IP models?'"
http://chipdesignmag.com/sld/blog/2010/07/22/why-open-source-matters/
Atrenta in System-Level Design, (7/22/2010)
'Good' Vs. 'Good Enough'
by Ed Sperling
"The decision for when a chip is ready for tapeout is changing—both in time and sometimes in terms of who's actually making that decision—as the amount of software being developed by hardware companies continues to grow."
http://chipdesignmag.com/sld/blog/2010/07/22/good%e2%80%99-vs-%e2%80%98good-enough%e2%80%99/
Atrenta in Test & Measurement World, (6/15/2010)
Atrenta hosts 3-D SoC design flow demo
by Rick Nelson
"Atrenta, AutoESL, Qualcomm, and IMEC have been collaborating on 3-D chip design, and they demonstrated what might be called a working prototype front-end 3-D
chip design system June 14 at the Design Automation Conference at Atrenta's booth."
http://www.tmworld.com/blog/Taking_the_Measure/39312-Atrenta_hosts_3_D_SoC_design_flow_demo.php
Atrenta in EDACafe, (10/29/2009)
Technical Paper: Verification of Multi-Clock Designs
"This white paper outlines a holistic approach to resolving issues associated with ever increasing numbers of clock interfaces, where data is
transferred between clocks of different frequencies and often between asynchronous domains."
http://www10.edacafe.com/link/display_detail.php?link_id=29617
Atrenta in Low-Power Engineering, (6/10/2010)
Experts at the Table: Nice to Have Vs. Need to Have
"Complexity is driving need to have for better up-front planning, better IP re-use, more things like verification IP and standards interfaces."
http://chipdesignmag.com/lpd/blog/2010/06/10/experts-at-the-table-nice-to-have-vs-need-to-have/
Atrenta in System-Level Design, (6/2/2010)
Experts at the Table: Problems to Solve in 3D Stacking
by Ed Sperling
"The mainstream world is not starting to think about 3D yet, but the large companies have either done it or are actively thinking about it."
http://chipdesignmag.com/sld/blog/2010/06/04/experts-at-the-table-problems-to-solve-in-3d-stacking-3/
Atrenta in IC Design and Verification Journal, (6/1/2010)
Escaping from the Silo: Fixing the 'Anti-Social' World of EDA Tools
by Ron Craig, Senior Marketing Manager Atrenta
"As a chip designer and EDA tool user, it's imperative to see the broader picture when using any tool which modifies your design in any way.
If the tools you are using aren't playing ball, maybe it's time to ask for better tools."
http://icjournal.com/icjournal/articles/20100601-atrenta/
Atrenta in EDA DesignLine, (5/26/2010)
Atrenta, AutoESL claim working 3D design flow
by Anne-Francoise Pele
"…the design flow is presented as the early version of a working system that addresses 3D-aware high-level synthesis, early partitioning, floorplanning
and multi-domain analysis."
http://www.edadesignline.com/showArticle.jhtml?articleID=225200219
Atrenta in System-Level Design, (5/21/2010)
Experts At The Table: Problems To Solve In 3D Stacking
by Ed Sperling
"The business need and the technical need for 3D is real.…When you look at the complexity on one side and the parasitics on the other, both of those
say you need to have some sort of 3D technology moving forward. The process enhancement has been happening and 3D technology is coming to the point where
it can become mainstream."
http://chipdesignmag.com/sld/blog/2010/05/21/experts-at-the-table-problems-to-solve-in-3d-stacking/
Atrenta in System-Level Design, (4/22/2010)
Timing Bomb
by Ed Sperling
"Timing closure, a basic operation in chip design and development, is becoming anything but basic at advanced process nodes."
http://chipdesignmag.com/sld/blog/2010/04/22/timing-bomb/
Atrenta in Chip Design, (3/2010)
SoC Designers Must Have Tangible Quality Metrics for Semiconductor Intellectual Property
by Piyush Sancheti, Senior Director of Business Development
"Simply stated, there are two major classes of design quality. A design or IP must meet its functional requirements and adhere to the protocol or
spec which it was intended for. But also, the IP must successfully integrate with the chip or sub-system it is was designed for."
http://chipdesignmag.com/display.php?articleId=4028
Atrenta in Chip Design, (2-3/2010)
Power-Optimization Solution Serves Ubiquitous RTL Designer
by Kiran Vittal, Product Marketing Director Atrenta
"Today's power-smart RTL designers use an “explicit enable
signal" coding style in their VHDL or Verilog designs.
This approach allows power-synthesis tools to insert clockgating
logic on these explicit enables. However, such tools
do not do the computation of the differential power savings
for each enable."
Excerpt from Chip Design Magazine Feb-Mar 2010
Altos Design Automation in Chip Design, (2/16/2010)
Thanks for The Memories But…
by Jim McCanny, CEO Alto Design Automation
"For challenging low-power and/or high performance designs, instance based characterization is a requirement to get the most out of the under-lying
silicon process and to truly manage timing and power. In short, tell you’re your IP supplier thanks for the memories, no thanks for the models and
take charge of creating the memory models you need yourself."
http://chipdesignmag.com/display.php?articleId=3947
Atrenta in EDA DesignLine, (2/10/2010)
EDA: Aging or dying?
by Mike Gianfagna, VP Marketing Atrenta
"It is unreasonable to believe that the current technology revolution in the consumer market will continue while EDA dies. Let's agree to stop
predicting the death of this important business and rather debate how it will mature (and grow)."
http://www.edadesignline.com/showArticle.jhtml?articleID=222700693
Atrenta in EDA DesignLine, (2/10/2010)
EDA DesignLine Engineering Guest Blog
by Mike Gianfagna, VP Marketing Atrenta
"EDA: Aging or dying?...It is unreasonable to believe that the current technology revolution in the consumer market will continue while EDA dies.
Let's agree to stop predicting the death of this important business and rather debate how it will mature (and grow)."
http://www.edadesignline.com/guest_
blogs/;jsessionid=5C5AQ4KCXS1B
1QE1GHRSKHWATMY32JVN
Altos Design Automation in Chip Design, (1/2010)
Designers—Start Your Characterization Engines
by Jim McCanny, CEO Altos Design Automation
"To get the most out of process technologies coming on line right now, designers need to radically re-think their strategies for timing closure.
The additional burdens of accounting for process variability, managing leakage and hitting a low power budget make obtaining market leading performance extremely difficult."
http://chipdesignmag.com/display.php?articleId=3893
Paul McLellan in Electronic Design (1/7/10)
To Shake Its Malaise, EDA Must Look To Where Design Is Really Happening
by Paul McLellan
"EDA is in trouble. It has become a fat change-averse business in a fast-changing environment. Even as the electronic system market is growing strongly, it is fragmenting."
http://electronicdesign.com/content.
aspx?topic=to_shake_its_malaise_
eda_must_look_to_where_design_
is_really_happening&catpath=eda
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