 |
 |
Technology Leadership Archives
Atrenta in Chip Design (10-11/09)
What EDA Needs to Do to Start Growing Again
by Mike Fazeli, VP Strategic Development Atrenta
"The chip guys take a broad, integrated approach to product development. That’s exactly the approach that the EDA industry needs to adopt to
start growing again."
Excerpt from Chip Design Magazine Oct-Nov 2009 (PDF)
Atrenta in Low-Power Design, (10/15/2009)
Experts At The Table: What's Next? (part 3/3)
by Ed Sperling
"Low-Power Design sat down with Leon Stok, EDA director for IBM's System & Technology Group; Antun Domic, senior vice president and general manager of Synopsys' Implementaton Group;
Prasad Subramaniam, vice president of design technology at eSilicon, and Bernard Murphy, chief technology officer at Atrenta."
http://chipdesignmag.com/lpd/blog/2009/10/15/experts-at-the-table-what%e2%80%99s-next-2/
Atrenta in Low-Power Design, (10/2/2009)
Experts At The Table: What's Next? (part 2/3)
"Low-Power Design sat down with Leon Stok, EDA director for IBM's System & Technology Group; Antun Domic, senior vice president and general manager of Synopsys' Implementaton Group;
Prasad Subramaniam, vice president of design technology at eSilicon, and Bernard Murphy, chief technology officer at Atrenta."
http://chipdesignmag.com/lpd/blog/2009/10/02/experts-at-the-table-whats-next/
Jim Hogan in EE Times, (9/18/2009)
Optimization key to the future, says EDA pioneer
by Dylan McGrath
"The greatest opportunity for EDA lies in providing optimization for system-on-chip designers as opposed to more functionality, according to a long-standing veteran of EDA."
http://www.eetimes.com/showArticle.jhtml;jsessionid=C421QKJIGDJKBQE1GHRSKH4ATMY32JVN?articleID=220001187
Atrenta in Low-Power Design, (9/17/2009)
Experts At The Table: What's Next? (part 1/3)
"Low-Power Design sat down with Leon Stok, EDA director for IBM's System & Technology Group; Antun Domic, senior vice president and general manager of Synopsys' Implementaton Group;
Prasad Subramaniam, vice president of design technology at eSilicon, and Bernard Murphy, chief technology officer at Atrenta."
http://chipdesignmag.com/lpd/blog/2009/09/17/experts-at-the-table-what's-next/
Atrenta in Daniel Nenni blog (9/9/09)
Semiconductor Design and Manufacture Predictability
"...I was quite impressed by the BlogFest sponsored by Atrenta, an executive briefing for bloggers. Atrenta offered up CTO Bernard Murphy, VP Strategic
Development Mike Fazeli, EDA Visionary Jim Hogan, and VP of Marketing Mike Gianfagnia, for questions and comments in an open format. The combined
semiconductor experience of these guys is a staggering 100+ years. Even more impressive, Mike Fazeli’s LinkedIn profile shows 27 years with Texas
Instruments in various semiconductor design enablement roles."
http://danielnenni.com/2009/09/09/semiconductor-design-and-manufacture-predictability/
Altos Design Automation in Chip Design, (8/2009)
Designers—Start Your Characterization Engines
by Jim McCanny, CEO Altos Design Automation
"To get the most out of process technologies coming on line right now, designers need to radically re-think their strategies for timing closure.
The additional burdens of accounting for process variability, managing leakage and hitting a low power budget make obtaining market leading performance extremely difficult."
http://www.chipdesignmag.com/display.php?articleId=3583
Atrenta in EDA Design Line, (8/7/2009)
Verification generation of constraints
by Sanjay Churiwala and Guru Shinghatta, Atrenta, and Wei Jiang and Andrew Pua, Texas Instruments
"Texas Instruments and Atrenta authors highlight and discuss the importance of constraint validation early in the design flow, and analyze the impact of this validation approach on a real design."
http://www.edadesignline.com/showArticle.jhtml?articleID=219100467
Atrenta in EDA Design Line, (7/27/2009)
Changing SoC design methodologies to automate IP integration and reuse
by Sameer Patel, Sr. Director Marketing Atrenta
"Automated SoC assembly techniques have rapidly emerged as the standard approach for building today's complex SoC designs.
These solutions are enabling design teams to boost their productivity while lowering development costs.
At the same time, these advanced approaches are helping them meet the stringent time-to-market requirements in today's competitive global economy."
http://www.edadesignline.com/howto/esl/218600884
Atrenta in EE Times, (7/24/2009)
DAC preview: Power again takes center stage
by Dylan McGrath
"There is some effort to come up with a unified model," said Kiran Vittal, director of product marketing for Atrenta Inc. "I don't know how successful
that will be, but there are talks about that." Atrenta, like other smaller EDA vendors, supports both standards.
http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=218600492&pgno=3
Atrenta in Electronic Design, (7/23/2009)
46th DAC Is This July's San Francisco Treat (Page 1)
by David Maliniak
"At DAC, Atrenta will unveil a fully integrated tool suite that allows capture of a design at the specification, or request for quote (RFQ), phase and supports
iterative refinement throughout RTL development, resulting in a smooth and predictable handoff to the back-end implementation flow (Fig. 1)."
http://electronicdesign.com/Articles/ArticleID/21477/21477.html
Altos Design Automation in Electronic Design, (7/23/2009)
46th DAC Is This July's San Francisco Treat (Page 3)
by David Maliniak
"If you're a Spice user, you probably will want to check out Altos Design Automation's Liberate MX, an ultra-fast, general purpose library characterizer for
memories and custom macro blocks. The new tool generates instance-specific library models in Liberty format including advanced current source models for timing and noise (CCS and ECSM)."
http://electronicdesign.com/Articles/ArticleID/21477/21477.html
Atrenta in Chip Design, (7/2009)
Verification of Clock Domain Crossing in SoCs: Part Three of Three—Case Study
by Sanjay Churiwala and Sapan Garg, Atrenta, and Chirag Gupta and Paresh Joshi, Texas Instruments
"This is our experience using Atrenta’s SpyGlass-CDC product on one of our SoCs."
http://www.chipdesignmag.com/display.php?articleId=3485
Magma Design Automation in System-Level Design, (7/2/2009)
Experts At The Table: The Mixed Signal Challenge
by Ed Sperling
System-Level Design sat down to discuss mixed signal design with Robert Hum, VP and general manager of Mentor Graphics’ Deep Submicron Division;
Mar Hershenson, VP of product development in Magma’s custom design business unit; Eric Filseth, CEO of Ciranova, and John Stabenow,
group director for solution and product marketing at Cadence.
Part 1/3: http://chipdesignmag.com/sld/blog/2009/06/25/the-mixed-signal-challenge/
Part 2/3: http://chipdesignmag.com/sld/blog/2009/01/02/experts-at-the-table-the-mixed-signal-challenge/
Atrenta in DFTdigest, Blog post and comments (6/29/2009)
Spyglass MBIST - is it BIST? or something else…
"…I couldn't help but wonder, between the the memory IP companies that offer BIST insertion for their own memory macros and other DFT vendors
that sell BIST implementation tools for various embedded macros, what about this tool is different?"
http://www.dftdigest.com/feature/spyglass-mbist-is-it-bist-or-something-else/
Atrenta in Chip Design, (6/2009)
Verification of Clock Domain Crossing in SoCs: Part Two—SoC Characteristics
by Sanjay Churiwala and Sapan Garg, Atrenta, and Chirag Gupta and Paresh Joshi, Texas Instruments
"There are many characteristics of an SoC design which a CDC verification tool should be able to handle well. "
http://www.chipdesignmag.com/display.php?articleId=3407
Atrenta in Chip Design, (5/21/2009)
Verification of Clock Domain Crossing in SoCs: Part One—Tools and Needs
by Sanjay Churiwala and Sapan Garg, Atrenta, and Chirag Gupta and Paresh Joshi, Texas Instruments
"To avoid SoC failures in the field or delays in delivering the SoC (due to late detection of CDC issues), the selection of the right tool for CDC verification is
one of the essentials in setting up the right methodology for the SoC design."
http://www.chipdesignmag.com/display.php?articleID=3303
Atrenta in Chip Design, (4/12/2009)
Streamlining IP-based Chip Design
by Piyush Sancheti, Sr. Director of Business Development Atrenta
"IP quality is a hotly debated topic in the semiconductor industry with many aspects and varying perspectives, depending on whether you are a supplier or a consumer."
http://www.chipdesignmag.com/display.php?articleId=3208
Atrenta in Chip Design, (March/April 2009)
RTL Analysis is Critical for 45-nm Design Tapeouts
by Ramesh Dewangan and Satish Soman, Atrenta
"Today's platforms can help designers achieve early design closure and avoid respins."
http://www.chipdesignmag.com/display.php?articleId=3315&issueId=34
Atrenta in EETimes (3/27/2009)
Design quality enhances company survival
by Bernard Murphy, CTO Atrenta
"Like it or not, semiconductor design in the early 21st century has more in common with an assembly line than a research lab. An assembly line with occasional
checkpoints to "fix quality" would be down most of the time. That they function smoothly is only possible because manufacturing engineers know, in advance,
exactly how they define quality, and they continuously monitor and correct quality problems, at the source. This continuous monitoring is often labeled
continuous quality control (CQC)."
http://www.eetimes.com/showArticle.jhtml;jsessionid=W3CEM5HB4X3UCQSNDLPSKH0CJUNN2JVN?articleID=216401723&pgno=1
Atrenta in EDACafe (3/25/2009)
Viewpoint Article: Boosting SoC Design Productivity For The iPhone Generation
by Sameer Patel, Sr. Director Marketing Atrenta
"Semiconductor suppliers will need to start looking at alternative design techniques such as platform-based design and IP reuse to drive
down the cost of design starts and more importantly, amortize these costs over several applications (or generations thereof) in order to get the desired ROI."
http://www10.EDACafe.com/nbc/articles/view_article.php?section=CorpNews&articleid=670501
Breker Verfication Systems in Chip Design (10-11/08)
Now Is the Time to Fix Coverage Metrics
by Adnan Hamid
"A crisis is looming in functional-verification coverage metrics. The industry has no choice but to fix it now. Otherwise—in light of more logic and processor
cores being squeezed into a single product—complex system-on-a-chip (SoC) design could very well come to a screeching halt."
http://chipdesignmag.com/display.php?articleId=3049&issueId=32
Breker Verfication Systems in System-Level Design Community (10/8/08)
Quality Time?
by Ed Sperling
"We need to build coverage around the outcomes you've got to test for and the constructs that will give you these applets. We also see that people
need to be able to verify their IP cores faster. The third thing is vertical re-use. We want to be able to test pieces of firmware to work with our
systems."
http://chipdesignmag.com/sld/blog/2008/10/08/quality-time/
Atrenta in SOCcentral (10/6/08)
When Silicon Processes Shrink, Test Needs Expand
by Mike Donlin
"Some EDA vendors are tackling DFT issues in the earlier phases of the design cycle by focusing on RTL. They say that
analyzing and fixing weak areas at the RTL can help designers pin-point problems early on, which can help them avoid
costly iterations."
http://www.soccentral.com/results.asp?EntryID=27014
Atrenta in EDA Design Line (9/29/08)
http://www.edadesignline.com/showArticle.jhtml;jsessionid=EBHHSQ14RPZAWQSNDLOSKHSCJUNN2JVN?
articleID=210604437&queryText=piyush+sancheti
in EE Times (9/29/08)
http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=210604484
and in Design & Reuse (9/29/08)
http://www.design-reuse.com/articles/19187/semiconductor-ip-quality.html
Measuring Quality in Semiconductor IP
by Piyush Sancheti
"I propose an approach for communicating design intent and measuring IP quality that is rooted in how design is done. The general premise
is to capture good design practices, known design killers and productivity detractors into a knowledge base that spans coding guidelines,
synthesizability, connectivity, portability, interfaces, timing, congestion, power, clocking, testability, etc."
Breker Verfication Systems in Electronic Design (9/11/08)
Verification Evolves Into Lean, Mean Bug-Stomping Machines
by David Maliniak
"Breker Verification Systems’ approach was forged in the company’s roots inside Advanced Micro Devices. 'In CPUs, random testing
never made sense,' says Hamid. 'We went to directed test cases and started using a graph-based approach. Now the big breakthrough
was to combine graphs with a constraint solver.'"
http://electronicdesign.com/Articles/ArticleID/19624/19624.html
Atrenta in SCDsource (Special Report: Low Power Design, 9/08 Issue 1)
Automating Low Power Design—A Progress Report
by Richard Goering
"STMicroelectronics is actively working
on an ESL flow for low-power design…using high-level, power-aware synthesis from Mentor Graphics and
Synfora, and is working with Atrenta to develop a high-level power
estimation tool."
Download Report (PDF)
Breker Verfication Systems in EDA DesignLine (5/6/08)
Host Bus Adapter (HBA) Verification with Trek
by Adnan Hamid, Beker Verification Systems
"In this approach, the constraint solver is used to randomly set stimulus values for each input port that satisfies the constraints.
The challenge with this approach is that a significant amount of control code must be written to create the right set of constraints
to be applied for each scenario to generate test cases of interest."
http://www.edadesignline.com/showArticle.jhtml;jsessionid=J4JSBZ4FYIGD2QSND
LPSKH0CJUNN2JVN?articleID=
207501891&queryText=breker+verification+systems
Breker Verfication Systems in Chip Design (3/08)
Nightmares in Functional Verification
by Ed Sperling
"Why do engineers really spend so many cycles trying to fix bugs, and is there a better solution?" (DesignCon 2008 panel discussion)
http://www.chipdesignmag.com/display.php?articleId=2166&issueId=27
Knowlent in SCD Source (2/8/08)
Analog experts call for new methodologies
by Tets Maniwa
"An explosion in analog/mixed-signal complexity will drive significant changes in analog design and verification methodologies, according to
panelists at DesignCon 2008."
http://scdsource.net/article.php?id=108
Knowlent Corporation in DACeZine (1/08)
Why Is Analog So Difficult?
by Ed Sperling
"EDA vendors and customers square off on what needs to be done to automate analog design flows; custom designs still plague sector."
Panel discussion with James Lin, Steven Lewis, Shrenik Mehta, and Sandipan Bhanot.
http://www.dac.com/45th/DACEzineJanuary2008-EdArticle.html
Knowlent Corporation in EDA DesignLine (1/7/08)
Why we need an analog design flow that's like digital now
by Nelson Seiden, Vice president, marketing and business development, Knowlent Corporation
"This new analog-mixed signal design imperative is challenged by ever-shorter development schedules, increasing price pressures, smaller
geometry foundry processes (which yield lower cost chips in mass volumes) with increasingly-magnified up front development costs and the
absolute need for first-time-right design methodology."
http://www.edadesignline.com/205210265
Breker Verification Systems in EDN (12/14/07)
EDN Hot 100 Products of 2007
Click on EDA in the list
Then click on Breker Verification Systems: for the first article "Predictable Path to 100% Verification Plan Coverage. Guaranteed."
Click on Trek functional-test-synthesis tool for the second article "EDA start-up Breker has a plan for better IC verification,"
by Michael Santarini, in EDN, 5/23/2007
Anchor Semiconductor in Solid State Technology (10/07)
DFM: What's real now?
by Chenmin Hu, President, Anchor Semiconductor Inc.
"DFM is actually thriving-providing value, achieving profit, garnering users and getting into manufacturing as well as design flows."
http://sst.pennnet.com/display_article/307851/5/ARTCL/none/none/DFM:-What%E2%80%99s-real-now?/
Altos Design Automation in Electronic Design (9/27/07)
Industry Ready To Sign On To Statistical Timing Signoff
by David Maliniak
"While corner-based signoff methodologies still reign supreme, an infrastructure to support statistical timing analysis is beginning to take shape."
http://electronicdesign.com/Articles/ArticleID/16788/16788.html
Altos Design Automation in EE Times (7/9/07)
SOS for sinking design flow methodology
invited commentary by Jim McCanny, CEO, Altos Design Automation Inc.
"A key challenge of the new flow is creation of statistical cell models in which each cell is characterized for its sensitivity to
both systematic and random variation....there are new, smarter characterization
methods that can keep the statistical-timing characterization run-times close to the run-time of static timing cell characterization, thus
keeping costs manageable."
http://www.eetimes.com/showArticle.jhtml?articleID=200900636&pgno=1
Breker Verification Systems in EE Times (5/28/07)
Products line up for DAC debut
"What's new: Trek, a graph-based functional test synthesis tool that lets users develop a verification plan, and then automatically
generates functional test vectors from it."
http://eetimes.com/news/design/showArticle.jhtml?articleID=199702007
Breker Verification Systems and Nanovata Design Automation in EE Times (5/28/07)
Toolmakers look to fix bottlenecks, fill gaps
by Richard Goering
"Startup Breker Verification Systems...claims its Trek is the first commercial graph-based functional test synthesis tool.
Startup Nanovata Design Automation will discuss its upcoming 'interconnect optimization' technology, which can take a layout and improve timing,
signal integrity, yield and manufacturability."
http://www.eetimes.com/news/design/showArticle.jhtml?articleID=199702008
Altos Design Automation and Anchor Semiconductor in Chip Design Magazine (2-3/07)
DFM Deathwatch? Or Does D Really Come Before M?
by Jim McCanny, CEO, Altos Design Automation Inc. and
Chenmin Hu, President, Anchor Semiconductor Inc.
"DFM's promise is quite promising. DFM will hit its stride and add unique value with manufacturing-intended DFM vendor tools that target the
manufacturers, such as foundries and IDMs."
http://www.chipdesignmag.com/print.php?articleId=1142?issueId=21
Altos Design Automation in Electronic News (2/9/07)
Who will be left standing in DFM?
Electronic News/Electronic Business Editor in Chief Ed Sperling and EDN Executive Editor Ron Wilson sat down to discuss the future of
design for manufacturing (DFM) with Jim McCanny, CEO of Altos Design Automation, Atul Sharan, president and CEO of Clear Shape
Technologies, and Jim Hogan, a private investor and EDA expert.
http://www.edn.com/article/CA6415131.html?partner=enews
Anchor Semiconductor in EE Times (2/9/07)
Commentary: DFM difficult, but no 'deathwatch'
by Chenmin Hu, President, Anchor Semiconductor, Inc.
"Design for manufacturability (DFM) startups are not headed for a DFM deathwatch, says Chenmin Hu of Anchor Semiconductor."
http://eetimes.com/news/design/showArticle.jhtml?articleID=197004930
Knowlent in Planet Analog (9/29/06)
What does it take for analog/mixed-signal signoff?
by Sandipan Bhanot, President and CEO, Knowlent Corporation
"Analog/mixed-signal EDA and signoff need to use the latest ideas and tools to be efficient and successful."
http://www.planetanalog.com/showArticle.jhtml?articleID=193100687
Knowlent in EDN (5/11/06)
Designers cast a skeptical eye on mixed-signal SOCs
by Ron Wilson, Executive Editor
"The functions are necessary, but integration challenges keep analog IP out of the mainstream for SOC design."
http://www.edn.com/article/CA6330094.html?industryid=2281
Knowlent in Chip Design (5/06)
Analog Wireless Chips: Have We Designed Ourselves Off A Cliff?
by Sandipan Bhanot, President and CEO, Knowlent Corporation
"We are creating such complex designs these days that we can't verify them. We're at a crisis in analog verification, impelled by
the insatiable need for chips in wireless applications. To continue meeting the demands of the wireless world, we must find a way
to get out of this crisis."
http://www.chipdesignmag.com/display.php?articleId=419&issueId=0
Knowlent in Chip Design (4-5/06)
Analog-RF IP Integration Challenges SoC Designers
by John Blyler
"At 90-nm and below geometries, designers of SoCs with analog and RF IP face a new set of issues. Foremost among these challenges is
the process variation in the manufacturing of silicon. The core has to be verified across the spectrum for this variability. Typically,
not all cases can be covered due to slow simulation speed, schedule pressures, and lack of automation, explains Sandipan Bhanot, CEO of
Knowlent Corp. (www.knowlent.com)."
http://www.chipdesignmag.com/display.php?articleId=435&issueId=16
|
|
