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Product Rollouts
Atrenta in Test & Measurement World (8/1/2009)
RTL approach supports memory BIST and repair insertion
by Rick Nelson, Editor-in-Chief
"Traditionally, you would implement MBIST and repair functionality for SOC designs at the gate level. But now you can use an approach that inserts MBIST and repair at the RTL."
http://www.tmworld.com/article/CA6673311.html?nid=3371&rid=8974136
Atrenta in EDA DesignLine (7/27/2009)
Atrenta extends platform for chip architecture designs
by Nicolas Mokhoff
"Atrenta Inc. has made major extensions to its 1Team-Genesis platform, which supports architectural level chip assembly."
http://www.edadesignline.com/products/218600866
Atrenta in EDA DesignLine (6/22/2009)
STMicroelectronics' design kit has memory BIST/repair
"STMicroelectronics has released Atrenta's SpyGlass-MBIST (memory built-in self test) insertion solution as part of its front-end design kit.
This kit is accessible to all ST design teams worldwide as well as ST's ASIC customers."
http://www.edadesignline.com/products/218100733
Atrenta in Tech-On (6/27/08, Japanese)
[DAC 2008] - SpyGlass (Atrenta, US) Ease of use improved by "Carefully chosen rules selected by use"
Arenta announced two new products at the Design Automation Conference (DAC 2008). The company is well known for the EDA tool,
SpyGlass, used to check RTL design data. The first product, Guideware, is a compilation of rules that SpyGlass products use for checking.
The other product is 1Team-Genesis. This can be considered a further-developed version of the Prototyping tool, 1Team Implement.
With 1Team-Genesis, specifications are estimated at a higher level (architecture level) compared with 1Team Implement which made estimates at RTL.
http://techon.nikkeibp.co.jp/article/NEWS/20080627/154026/?ST=edaonline
Atrenta in EDN (6/19/08)
Atrenta announces 1Team-Genesis, collaborates with STMicroelectronics
by Rick Nelson, Editor-in-Chief
"Atrenta Inc announced at the 45th DAC (Design Automation Conference) the availability of 1Team-Genesis, which focuses on the capture
of design specifications, the automated generation of design descriptions and documentation, the rapid exploration of design alternatives,
and 'correct-by-construction' chip assembly."
http://www.edn.com/index.asp?layout=article&articleid=CA6571551
Breker Verfication Systems in EDA DesignLine (5/6/08)
Host Bus Adapter (HBA) Verification with Trek
by Adnan Hamid, CEO and founder of Breker Verification Systems
"The value of Trek is that it can generate deep state scenario from the Coverage Model and guarantee coverage closure. Trek connects into the low level
Testbench at the BFM level or at the wire level using a C-API. When the BFM or the simulator requires a new scenario, a call to Trek is made in a
similar fashion to how a directed test case is submitted to the testbench."
http://www.edadesignline.com/showArticle.jhtml;jsessionid=J4JSBZ4FYIGD2QSNDLPSKH0CJUNN2JVN?
articleID=207501891&queryText=breker+verification+systems
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