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Product Rollouts
Atrenta in Test & Measurement World (8/1/2009)
RTL approach supports memory BIST and repair insertion
by Rick Nelson, Editor-in-Chief
"Traditionally, you would implement MBIST and repair functionality for SOC designs at the gate level. But now you can use an approach that inserts MBIST and repair at the RTL."
http://www.tmworld.com/article/CA6673311.html?nid=3371&rid=8974136
Atrenta in EDA DesignLine (7/27/2009)
Atrenta extends platform for chip architecture designs
by Nicolas Mokhoff
"Atrenta Inc. has made major extensions to its 1Team-Genesis platform, which supports architectural level chip assembly."
http://www.edadesignline.com/products/218600866
Atrenta in EDA DesignLine (6/22/2009)
STMicroelectronics' design kit has memory BIST/repair
"STMicroelectronics has released Atrenta's SpyGlass-MBIST (memory built-in self test) insertion solution as part of its front-end design kit.
This kit is accessible to all ST design teams worldwide as well as ST's ASIC customers."
http://www.edadesignline.com/products/218100733
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