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Product Rollout Archives
Atrenta in Tech-On (6/27/08, Japanese)
[DAC 2008] - SpyGlass (Atrenta, US) Ease of use improved by "Carefully chosen rules selected by use"
Arenta announced two new products at the Design Automation Conference (DAC 2008). The company is well known for the EDA tool,
SpyGlass, used to check RTL design data. The first product, Guideware, is a compilation of rules that SpyGlass products use for checking.
The other product is 1Team-Genesis. This can be considered a further-developed version of the Prototyping tool, 1Team Implement.
With 1Team-Genesis, specifications are estimated at a higher level (architecture level) compared with 1Team Implement which made estimates at RTL.
http://techon.nikkeibp.co.jp/article/NEWS/20080627/154026/?ST=edaonline
Atrenta in EDN (6/19/08)
Atrenta announces 1Team-Genesis, collaborates with STMicroelectronics
by Rick Nelson, Editor-in-Chief
"Atrenta Inc announced at the 45th DAC (Design Automation Conference) the availability of 1Team-Genesis, which focuses on the capture
of design specifications, the automated generation of design descriptions and documentation, the rapid exploration of design alternatives,
and 'correct-by-construction' chip assembly."
http://www.edn.com/index.asp?layout=article&articleid=CA6571551
Breker Verfication Systems in EDA DesignLine (5/6/08)
Host Bus Adapter (HBA) Verification with Trek
by Adnan Hamid, CEO and founder of Breker Verification Systems
"The value of Trek is that it can generate deep state scenario from the Coverage Model and guarantee coverage closure. Trek connects into the low level
Testbench at the BFM level or at the wire level using a C-API. When the BFM or the simulator requires a new scenario, a call to Trek is made in a
similar fashion to how a directed test case is submitted to the testbench."
http://www.edadesignline.com/showArticle.jhtml;jsessionid=J4JSBZ4FYIGD2QSNDLPSKH0CJUNN2JVN?
articleID=207501891&queryText=breker+verification+systems
Knowlent in EE Times (6/19/06)
Language aids analog testbench development
by Richard Goering
"While many products help automate digital IC verification, the Knowlent Corp. Opal platform is one of the few that focuses on analog
verification. Knowlent this week will add a proprietary language, dubbed Viper, that helps users develop testbenches that are independent
from their designs."
http://eetimes.com/news/design/showArticle.jhtml?articleID=189500282
Knowlent in Electronic Design (6/19/06)
Testbench Platform And Language Take On Analog Signoff
by David Maliniak
"Designers have had access to digital verification IP for years now. But until recently, analog designers have not had the use of analog
verification IP. Knowlent provides testbench setups and data collection for each measurement in the PCI Express specification, enabling
analog designers to obtain consistent and complete coverage."
http://www.elecdesign.com/Articles/Index.cfm?AD=1&AD=1&ArticleID=12881
Optimal in EDACafe (EDAWeekly Review) (11/21-25/05)
The Optimal Solution
by Jack Horgan
"The weekly editorials have covered several vendors in the power integrity field. Some have attacked the issue through power management
and some though power grid design. Optimal offers products with complete signal integrity and power integrity design flow from IC to
Package to PCB."
http://www10.edacafe.com/nbc/articles/view_weekly.php?articleid=224585
Optimal in EE Times (1/17/05)
Power tool unites package, pcb
by Richard Goering
"Printed-circuit-board designers are having severe problems with IC packages that don't work once they're placed on a board.
Optimal Corp. this week will offer a solution with PowerGrid, a power integrity analysis tool aimed at designers of both IC packages and
pc boards."
http://www.eetimes.com/article/showArticle.jhtml?articleId=57701383
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