 |
 |
New Company Introductions Archives
Breker Verification Systems in DeepChip (12/18/08)
Breker CEO explains his graph-based "intelligent testbench" tool ESNUG 478 Item 4
"Breker is in the 'intelligent testbench' arena. We approach verification
planning/automated test case generation through what we call graph-based
scenario planning (that we deliver in our Trek product.)"
http://www.deepchip.com/items/0478-04.html
Breker Verification Systems in Tech-On (6/18/07)
< DAC 2007 > Functional verification pattern compilation tool utilizing graph-based technology from the United States company, Breker
by Kojima Ikutarou, Nikkei Micro Devices
"Breker Verification Systems, Inc., which invented the graph-based functional verification pattern compilation technique, has developed the EDA tool
"Trek." The tool was introduced at the 44th Design of Automation Conference (DAC 2007)."
http://techon.nikkeibp.co.jp/article/NEWS/20070618/134419/ (in Japanese)
English translation (pdf)
Nanovata Design Automation in EE Times (5/23/07)
Routing experts launch 'interconnect synthesis' startup
by Richard Goering
"The founders of startup Nanovata Design Automation helped develop some of the best-known IC layout products in the world, including Apollo,
Astro and Columbia from Avanti Corp. Now they've banded together to provide 'interconnect synthesis' technology that optimizes IC layouts
for timing, signal integrity, yield and manufacturability."
http://www.eetimes.com/showArticle.jhtml;jsessionid=KJXLQJ3DTPH2CQSNDLOS
KH0CJUNN2JVN?articleID=199701573
Breker Verification Systems in EDN (5/23/07)
EDA start-up Breker has a plan for better IC verification
by Michael Santarini
"Breker Verification Systems wants to help you reduce the amount of testbench generation and overall verification you need to do by helping you create a comprehensive IC-verification plan upfront in the functional-verification process and to help you drive better test vectors into your current verification environment."
http://www.edn.com/article/CA6445807.html
Breker Verification Systems in EE Times (5/14/07)
IC verification startup takes graphical approach to test generation
by Richard Goering
"Breker Systems this week will introduce both itself and its first product, Trek, claimed to be the first commercial
graph-based functional test synthesis tool."
http://eetimes.com/news/design/showArticle.jhtml;jsessionid=X3ELDETXOKYLEQSNDLPCK
HSCJUNN2JVN?articleID=199500320
FRONT PAGE NEWS
Altos Design Automation in EE Times, Latest News (7/3/06)
Statistical timing revs for 45-nm era
by Richard Goering
"Statistical timing analysis may represent the next major technology shift in nanometer IC implementation, but it's going nowhere
fast without statistical timing models. Jim McCanny, CEO of startup Altos Design Automation Inc., believes he has a solution that
will make statistical timing feasible."
http://eetimes.com/news/latest/showArticle.jhtml?articleID=189800223
Altos Design Automation in EE Times, Design News (7/3/06)
Cell model creation for statistical timing analysis
by Ken Tseng, CTO, Altos Design Automation, and Kelvin Le, Technical Staff, Extreme DA
"Statistical static timing analysis (SSTA) offers a number of advantages over traditional corner based static timing analysis.
Most notably, it provides a more realistic estimation of timing relative to actual silicon performance. Armed with a better answer,
designers can focus their optimization efforts on the timing paths that have the biggest impact on overall performance and yield
rather than paths that may fail only at extreme corners."
http://eetimes.com/news/design/showArticle.jhtml?articleID=190100003
Altos Design Automation in Electronic News (7/3/06)
Altos Targets Statistical Timing Models
by Staff Reporter
"To develop new cell characterization tools for IC designers working on complex SoCs at 90nm, 65nm and 45nm process
technologies Altos Design Automation Inc. has been formed with emphasis on the creation of statistical timing models."
http://www.reed-electronics.com/electronicnews/article/CA6349240.html?text=Altos
|
|
